Difference between revisions of "LDC inline IR"
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The file [https://github.com/ldc-developers/druntime/blob/ldc/src/ldc/simd.di ldc.simd] contains the source for the LLVM vector instructions. | The file [https://github.com/ldc-developers/druntime/blob/ldc/src/ldc/simd.di ldc.simd] contains the source for the LLVM vector instructions. | ||
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Revision as of 13:35, 26 February 2014
LDC has an interface to LLVM IR. This can be useful if you want to exploit special LLVM features like vector instructions or address space operations. Please be aware that LLVM IR is platform dependent. It is not a platform independent assembler!
Interface
To use the inline IR feature you have to declare the following magic template:
pragma(LDC_inline_ir)
R inlineIR(string s, R, P...)(P);
The first type parameter contains the IR and the second the return type. Then follows the types of the parameters. The parameters are passed as usual.
Inside the IR you refer to the parameters with the special names %0, %1 and so on.
Examples
Using another address space
On Windows 64bit, the bottom of stack is stored at gs:8. Instead of using inline assembler you can use this IR:
void* getStackBottom(){
return inlineIR!(`
%ptr = inttoptr i64 %0 to i64 addrspace(256)*
%val = load i64 addrspace(256)* %ptr, align 1
%tmp = inttoptr i64 %val to i8*
ret i8* %tmp`,
void*, ulong)(8);
}
LLVM uses different address spaces to model the segment registers on x86/x86_64. The address space 256 is the gs segment register and address space 257 is the fs segment register.
Using vector instructions
The file ldc.simd contains the source for the LLVM vector instructions.